| 0.4V의 초저전압에서 SRAM 동작 실현 | |||||||
| KISTI 미리안『글로벌동향브리핑』 2011-12-14 | |||||||
최근 휴대기기나 서버, 네트워크 관련기기 등 다양한 분야의 기기에서 소비전력을 억제하는 것은 매우 중요한 과제 중의 하나이다. 저소비전력화를 위한 최대의 요인은 전원전압을 줄이는 것으로서, 130nm 공정까지는 정상적으로 전원전압을 줄일 수 있었다. 하지만 그 이후 28nm 공정에 이르기까지 최근에는 1V 근방에서 더 줄어들고 있지 않은 상황이다. 전원전압의 절감을 막는 가장 큰 원인 중의 하나는 내장형 SRAM의 동작 전압이다. SuVolta의 파워슈링크 기술의 하나인 DDC 트랜지스터[주2]와 후지츠 세미컨덕터가 보유한 고도의 프로세스 기술을 접목함으로써 트랜지스터의 문턱전압의 편차를 종래의 절반 이하로 줄이고 576Kb의 내장형 SRAM에서 약 0.4V의 매우 낮은 동작전압에서의 동작 확인에 성공하였다. 이 기술은 시스템 LSI에 이용되어 온 기존의 설계자산과 기존 장치 등을 그대로 활용할 수 있다는 점에서 더욱 의미가 있다. 미세화에 따라 CMOS 회로의 전원전압은 1V 정도까지 줄일 수 있지만, 동작시의 소비전력은 전압전압의 제곱에 비례하기 때문에 소비전력의 절감은 CMOS 회로에 있어서 매우 중요한 과제의 하나이다. 전원전원의 절감이 130nm 공정에서부터 정체되기 시작한 것은 RDF(random dopant fluctuation)을 포함하는 몇 가지 편차 발생 원인이 존재하기 때문이다. RDF란 불순물 원자의 위치와 밀도가 무질서하게 분포하는 것으로 이에 따라 트랜지스터의 문턱전압에 큰 편차가 발생하게 된다. 첨부의 그림 1은 후지츠 세미컨덕터의 저전력 CMOS 회로용 프로세스 기술을 이용하여 제조한 SuVolat의 DDC 트랜지스터 구조의 단면 TEM(transmission Electron Microscopy) 사진을 나타낸다. DDC 트랜지스터는 기존의 트랜지스터와 마찬가지로 실리콘 기판 위에 형성된다. 공동연구팀은 DDC 트랜지스터를 이용하여 내장형 SRAM이 0.425V에서도 동작한다는 것을 실증하였다. 대부분의 제품에서 전원전압의 하한은 내장형 SRAM의 안정적인 동작전압에 의해 결정되기 때문에 다양한 CMOS 회로를 탑재한 제품에서도 0.4V 근방에서 동작한다는 것을 실증한 셈이다. 한편, 이번 기술의 상세한 내용은 지난 주 워싱턴에서 개최된 반도체 디바이스 관련 학회인 IEDM(International Electron Devices Meeting)에서 보고되었다. [주1] 파워슈링크 (power shrink) 기술: SuVolta가 개발한 소비전력을 절감하는 기술의 총칭이다. DDC 트랜지스터와 이를 효과적으로 사용하는 회로 등을 포함한다. [주2] DDC 트랜지스터: Deeply Depleted Channel Transistor. 실리콘 기판 위에 복수의 불순물층을 포함하여 구성하는 것을 특징으로 한다. (그림1) DDC 트랜지스터의 단면 TEM 사진이다. (그림2) 576Kb의 내장형 SRAM의 수율을 전원전압의 함수로 나타낸 것이다. 수율은 576Kb 모두가 동작한 SRAM의 수로부터 계산하였다.
|
2011年12月7日
富士通セミコンダクター株式会社
SuVolta, Inc.
富士通セミコンダクター株式会社
SuVolta, Inc.
富士通セミコンダクターとSuVolta、SRAM動作を約0.4Vの超低電圧で実現
富士通セミコンダクター株式会社（本社：神奈川県横浜市、代表取締役社長：岡田 晴基、以下、富士通セミコンダクター）とSuVolta, Inc.（本社：米国カリフォルニア州、CEO兼社長：Bruce McWilliams、以下、SuVolta）は、SuVoltaの“パワーシュリンク技術(注1)”と富士通セミコンダクターの“低消費電力プロセステクノロジー”により、電源電圧が0.425Vという極めて低い電圧でSRAMを動作させることに成功しました。この両社の技術により、ICの消費電力を低減することができ、将来的には、超低消費電力製品（エコ製品）を提供することができます。詳細技術については、12月5日から7日まで米国ワシントンDCで開催される「IEDM（International Electron Devices Meeting）2011」学会にて報告されます。
携帯機器からサーバー、ネットワーク関連機器にいたる幅広い機器において、消費電力を抑えることは重要課題の一つになっています。低消費電力化への最大の要因は電源電圧で、130nmテクノロジーまでは定常的に電源電圧の低減がなされてきました。それ以降、28nmテクノロジーにいたるまで、1V近傍のまま低減されていません。電源電圧の低減を阻む最大の要因の一つは、組込み型SRAMの動作電圧です。
SuVoltaの“パワーシュリンク技術”の一つであるDDCトランジスタ(注2)と、富士通セミコンダクターの高度なプロセス技術を組み合わせることにより、両社はトランジスタのしきい値電圧の“ばらつき”を従来の約半分に低減し、576キロビット（以下、Kb）の組込みSRAMで約0.4Vという極めて低い電源電圧での動作確認に成功しました。本技術は、システムLSIに用いられている既存の設計資産や既存装置などをそのまま活用することができます。
背景
微細化に沿ってCMOS回路の電源電圧は1V程度まで下げることができましたが、この電源電圧の低減の流れは130nmテクノロジーまでで、それ以降の28nmテクノロジーにいたるまで電源電圧を1V以下に下げることができませんでした。動作時の消費電力は電源電圧の2乗に比例するため、消費電力削減はCMOS回路における重要な課題となっています。電源電圧の低減が130nmテクノロジーで停滞したのは、RDF（Random Dopant Fluctuation）を含むいくつかのばらつき要因が存在するためです。RDFとは、不純物原子の位置と密度のランダムな揺らぎのことで、これによりトランジスタのしきい値電圧に“ばらつき”が大きく生じます。
極薄膜SOI（Silicon on Insulator）トランジスタとフィン型トランジスタ構造により、RDFを劇的に改善できると報告されていますが、構造的に複雑であり、既存の設計資産や製造資産を利用することが困難と考えられました。
SuVoltaの DDCトランジスタ構造
図1．DDCトランジスタの断面TEM写真
図1.に、富士通セミコンダクターの低電力CMOS回路用プロセス技術を用いて製造した、SuVoltaのDDCトランジスタ構造の断面TEM（Transmission Electron Microscope）写真を示します。DDCトランジスタは、既存のトランジスタと同様にシリコン基板上に形成されます。
組込みSRAMによる電源電圧の低下と歩留まり
図2．576Kb組込みSRAMの歩留まりの
電源電圧依存推移
電源電圧依存推移
富士通セミコンダクターとSuVoltaは、DDCトランジスタにより、組込みSRAMが0.425Vでも動作することを実証しました。図2.に、その結果を示します。大半の製品における電源電圧の下限は、組込みSRAMの安定動作により決まるため、さまざまなCMOS回路を搭載した製品でも0.4V近傍で動作することを実証したことになります。
図2.は、576Kbの組込みSRAMの歩留まりを電源電圧の関数として示したものです。歩留まりは、576Kbすべてが動作した組込みSRAM数から歩留まりを計算しています。
商標について
- 記載されている製品名などの固有名詞は、各社の商標または登録商標です。
注釈
- 注1 パワーシュリンク技術:
- SuVoltaの開発した消費電力低減技術全般の総称であり、後述する DDCトランジスタとこれを効果的に使用する回路などを含みます。
- 注2 DDCトランジスタ:
- Deeply Depleted Channel transistor シリコン基板上に複数の不純物層を含み構成することを特徴とします。
本件に関する技術お問い合わせ先
報道関係者お問い合わせ先
Fax: 03-5159-2166December 7, 2011
Fujitsu Semiconductor Limited
SuVolta, Inc.
Fujitsu Semiconductor Limited
SuVolta, Inc.
Fujitsu Semiconductor and SuVolta Demonstrate Ultra-low-voltage Operation of SRAM Down to ~0.4V
YOKOHAMA, Japan, and LOS GATOS, Calif., December 7, 2011 - Fujitsu Semiconductor Limited and SuVolta, Inc. today announced that they have successfully demonstrated ultra-low-voltage operation of SRAM (static random access memory) blocks down to 0.425V by integrating SuVolta’s PowerShrink™ low-power CMOS platform into Fujitsu Semiconductor’s low-power process technology. By reducing power consumption, these technologies will make possible the ultimate in “ecological” products in the near future. Technology details and results will be presented at the 2011 International Electron Devices Meeting (IEDM) being held in Washington DC, starting December 5th.
Controlling power consumption is the primary limiter of adding features to product types ranging from mobile electronics to tethered servers and networking equipment. The biggest contributor to power consumption is supply voltage. Previously, the power supply voltage of CMOS steadily reduced to approximately 1.0V at the 130nm technology node, but it has not reduced much further as technology has scaled to the 28nm node. To reduce the power supply voltage, one of the biggest obstacles is the minimum operating voltage of embedded SRAM blocks.
By combining SuVolta’s Deeply Depleted Channel™ (DDC) transistor technology – a component of the PowerShrink platform – and Fujitsu Semiconductor’s sophisticated process technology, the two companies have verified that a 576Kb SRAM can work well at approximately 0.4V by reducing CMOS transistor threshold voltage (VT) variation to half. This technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools.
Background
Following scaling law, the power supply voltage of CMOS has been reduced progressively down to approximately 1.0V at the 130nm technology node. However, power supply voltages have remained at around 1.0V even though process technologies have continued to scale from 130nm to 28nm. Since dynamic power is proportional to the square of supply voltage, power consumption has become a primary issue for CMOS technology. Scaling of supply voltage stopped at the 130nm node because of multiple sources of variation including random dopant fluctuation (RDF). RDF is a form of device and process variation resulting from fluctuations in the concentration of the implanted dopant or impurity atoms in the transistor channel. RDF results in variation in threshold voltage (VT) between different transistors on a chip.
Successful reduction of RDF has been reported using two exotic structures, ETSOI and Tri-Gate – a FinFET technology. However, both ETSOI and FinFET technologies are complex, making them difficult to match with existing design and manufacturing infrastructures.
SuVolta’s DDC™ transistor
Figure 1. Cross-section of DDC transistor
An implementation of SuVolta’s DDC transistor on Fujitsu Semiconductor’s low-power CMOS process is shown in figure 1. The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure.
Reduction of minimum operating voltage for SRAM
Figure 2. Functional yield of 576k SRAM macro
For most chips, lowering supply voltage is limited by the SRAM. Fujitsu Semiconductor and SuVolta have demonstrated an SRAM macro functional even at 0.425V, as seen in figure 2. Since SRAM is the most challenging circuit for supply voltage reduction, the verification implies that DDC could enable approximately 0.4V operation across a variety of CMOS-based circuits.
Figure 2 shows yield of 576k SRAM macro as a function of supply voltage. The yield is calculated by counting macros in which all bits have passed.
Summary and Future Plans
The process flow for DDC transistors has been successfully established. Fabricated DDC transistors demonstrate a 50 percent reduction of VT variation from the baseline flow, and deliver functional SRAMs even at 0.425V. These show the DDC transistors’ capability to reduce supply voltage down to ~0.4V.
Fujitsu Semiconductor is going to advance the technology and aggressively respond to customers' requests for low-power consumption and/or low voltage operation in consumer products, mobile devices and other offerings.
About Fujitsu Semiconductor Limited
Fujitsu Semiconductor Limited designs, manufactures, and sells semiconductors, providing highly reliable, optimal solutions and support to meet the varying needs of its customers. Products and services include microcontrollers, ASICs, ASSPs, and power management ICs, with wide-ranging expertise focusing on mobile, ecological, automotive, imaging, security, and high-performance applications. Fujitsu Semiconductor also drives power efficiency and environmental initiatives. Headquartered in Yokohama, Fujitsu Semiconductor Limited (formerly named Fujitsu Microelectronics Limited) was established as a subsidiary of Fujitsu Limited on March 21, 2008. Through its global sales and development network, with sites in Japan and throughout Asia, Europe, and the Americas, Fujitsu Semiconductor offers semiconductor solutions to the global marketplace. For more information, please see:http://jp.fujitsu.com/fsl/en/.
About SuVolta, Inc.
SuVolta, Inc. develops and licenses scalable semiconductor technologies that enable a significant reduction in IC power consumption while maintaining performance. Based in Silicon Valley, the team includes world-class engineers and scientists with a long history of technology development and innovation to advance the semiconductor industry. The company is backed by leading venture capital firms Kleiner Perkins Caufield & Byers (KPCB), August Capital and NEA. For more information, visit www.suvolta.com.
Press Contacts
Fujitsu Semiconductor Limited:
Public Relations Department
Corporate Planning and Business Strategy Office
Inquiries
Public Relations Department
Corporate Planning and Business Strategy Office
InquiriesThe Hoffman Agency (SuVolta’s public relations agency) :
Amanda Crnkovich
Tel: +1-408-975-3015
E-mail: acrnkovich@hoffman.com
Amanda Crnkovich
Tel: +1-408-975-3015 E-mail: acrnkovich@hoffman.comTechnical Contacts
SuVolta, Inc.:
Learn more about SuVolta’s Deeply Depleted Channel (DDC) structure @ http://www.suvolta.com/cmos-power/
For more information on licensing the SuVolta technology, please go to http://www.suvolta.com/sales-inquiry/
Follow us on Twitter @ http://twitter.com/SuVoltaInc
Learn more about SuVolta’s Deeply Depleted Channel (DDC) structure @ http://www.suvolta.com/cmos-power/
For more information on licensing the SuVolta technology, please go to http://www.suvolta.com/sales-inquiry/
Follow us on Twitter @ http://twitter.com/SuVoltaInc
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